One type of memory known in the art is double data rate synchronous dynamic random access memory (DDR SDRAM). In general, DDR SDRAM includes at least one array of memory cells. The memory cells in the array of memory cells are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Conductive word lines extend across the array of memory cells along the x-direction and conductive bit lines extend across the array of memory cells along the y-direction. A memory cell is located at each cross point of a word line and a bit line. Memory cells are accessed using a row address and a column address.
DDR SDRAM uses a main clock signal and a data strobe signal (DQS) for addressing the array of memory cells and for executing commands within the memory. The clock signal is used as a reference for the timing of commands such as read and write commands, including address and control signals. DQS is used as a reference to latch input data into the memory and output data into an external device.
During a write operation, two bits, four bits, or another even number of bits are collected and processed in the memory at the same time to maximize the bandwidth of the memory. DQS is controlled by a memory controller and the data bits are collected on each transition of DQS. At the first clock rising edge after the final DQS falling edge, the collection of data bits ends and internal processing begins.
Once collection of the data bits is complete, the memory controller may no longer drive the DQS signal resulting in noise on the DQS signal line. This noise, referred to as post-amble DQS noise, may oscillate around the termination voltage of the data bus. If the post-amble DQS noise occurs before internal processing of the collected data begins, the collected data can be corrupted as transitions in the post-amble DQS noise latch in undefined data in place of valid data.